Markets AMD -1.35% JUL 23, 2026

AMD launches EPYC Venice and Helios rack at Advancing AI 2026, boxing Intel's Q2 print

Lisa Su unveiled the first x86 CPU on TSMC's 2nm node and a $5.25M Helios rack the same afternoon Intel reported Q2 results, framing a 12-month competitive gap.

BY HENLEY MARRAST · MARKETS DESK

Lisa Su walked onto the Moscone West stage Thursday morning and, over roughly two hours, boxed Intel into the worst possible framing for its own Q2 2026 print later that afternoon. AMD’s Advancing AI 2026 keynote introduced EPYC “Venice,” the first x86 server CPU on TSMC’s N2 node, alongside the Helios rack-scale system built around Instinct MI400-series GPUs. Intel reported after the close, at 2 p.m. PDT.

The scheduling wasn’t subtle. Intel guided Q2 revenue to $13.8B–$14.8B and non-GAAP EPS of $0.20, down from Q1’s $13.6B and $0.29. AMD spent the morning telling enterprise buyers they were about to face a roughly 12-month gap between Venice and Intel’s forthcoming Xeon “Diamond Rapids” on the Intel 18A-P node. Shares changed hands near $553, more than double where they started 2026.

Venice tops out at 256 cores and delivers about a 1.7x performance improvement over EPYC Turin. TSMC’s N2 process is the pitch underneath the pitch: densities above 310 million transistors per square millimeter, a 10% to 15% performance benefit over N3E at equivalent power, or a 25% to 30% power reduction at equivalent performance. Shipping begins in the second half of 2026.

Helios is where the strategic capture becomes explicit. Each rack packs 72 MI455X accelerators, 31 TB of pooled HBM4, 1.4 PB/s of aggregate memory bandwidth, 260 TB/s of scale-up interconnect, 43 TB/s of Ethernet scale-out via AMD Pensando silicon, 2.9 FP4 exaFLOPS of inference and 1.4 FP8 exaFLOPS of training. List: $5.25 million per rack.

The customer roll call did the rest of the work. Microsoft Azure committed to deploying Helios at scale across the HDv2 and HXv2 VM series. Oracle signed on. OpenAI and Meta together account for roughly 12 gigawatts of AMD accelerator capacity, a number that reframes AMD from challenger to structural counterparty. Sam Altman appeared alongside Su, which is its own form of narrative evidence.

Intel’s print landed into a room AMD had already furnished. The 2005–2006 Opteron cycle offers the closest institutional memory, and the resemblance is doing analytical work the earnings call couldn’t unwind.

Sources

About the author

Henley Marrast

MARKETS DESK

Henley Marrast covers AI-equity flow, accelerator demand, and earnings prints for AI Sheet Report. She leads coverage of the public AI complex from the New York markets desk, with a focus on the daily tape and quarterly results. She has been writing about technology markets for several years.